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DS1821
 
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1-Wire BUS SYSTEM
The 1-Wire bus system uses a single bus master (i.e., a microprocessor) to control slave devices. The
DS1821 functions as a slave device when it is used in 1-Wire mode; however, since the DS1821 is not
addressable or multi-droppable, a single 1-Wire-mode DS1821 must be the only slave device on the bus.
All data and commands are transmitted least significant bit first over the 1-Wire bus.
The following discussion of the 1-Wire bus system is broken down into three topics: hardware
configuration, transaction sequence, and 1-Wire signaling (signal types and timing).
 
HARDWARE CONFIGURATION
The 1-Wire bus has by definition only a single data line. Each device (in this case, the master and one
DS1821) interfaces to the data line via an open drain or 3state port. This allows each device to release
the data line when the device is not transmitting data so that the bus is available for use by the other
device. The 1-Wire port of the DS1821 (the DQ pin) is open drain with an internal circuit equivalent to
that shown in Figure 6.
The 1-Wire bus requires an external pullup resistor of approximately 5 k&; thus, the idle state for the 1-
Wire bus is high. If for any reason a transaction needs to be suspended, the bus MUST be left in the idle
state if the transaction is to resume. Infinite recovery time can occur between bits so long as the 1-Wire
bus is in the inactive (high) state during the recovery period. If the bus is held low for more than 480 祍,
the DS1821 will be reset.
 
HARDWARE CONFIGURATION Figure 6 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
TRANSACTION SEQUENCE
The transaction sequence for accessing the DS1821 via the 1-Wire port is as follows:
"   Initialization
"   DS1821 Function Command
"   Data Transmitted/Received
 糀
yp.
 
X
 
D 1  21 1-WIRE P  RT
100 &
 
R
X
 = RECEIVE
T
X
 = TRANSMIT 
DD
 
.7K
-wire bus
Q
in
Micro-
processor
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